This invention relates generally to the instruction set architectures (ISA) of processors. More particularly, the invention relates to operand data types for digital signal processors.
To process data in a computing device, an instruction set is defined. An instruction set having one or more instructions are required for computing devices such as microprocessors, computers or single chip DSP devices. In defining an instruction set for a computing device, the data type of operands that will be computed is usually predefined based on the number representation to be utilized and the type of hardware that is provided. The data type of the instruction set architecture (ISA) in essence is defined by how and what type of numeric data the computing device will process.
The number representation utilized for data types includes the radix or base of a number, whether or not it is to be encoded (binary coded such as BCD), and the numeric format. The radices ordinarily used in computers is binary or a radix of two. Other radices that may be used in computers is octal (radix of eight), decimal (radix of ten), and hexadecimal (radix of sixteen). If a radix other than two is selected, it ordinarily needs to be binarily coded so that it is recognizable by digital logic. For example, if a radix of ten is used the numbers are binary coded using a four bit binary number which is referred to as binary coded decimal (BCD).
The numeric format is associated with whether the number is to have a fixed point or floating point representation, an integer or fractional format and their associated representations, a normalized or unnormalized format, and whether the bits representing the number are packed or unpacked. In a floating point representation an exponent number is usually included. In a fixed point representation, the radix point (decimal point for radix of ten) is in a fixed position with respect to the bits or numbers of the data. If the radix point is to the right of all numbers it is an integer format. If the radix point is to the left of all numbers it is a fractional format. An example of floating point data types is the single and double precision floating point data types defined in the IEEE 754 specification.
The normalized and unnormalized formats are specific to floating point representations and a fractional format. If a number is to be normalized, the number is to be represented in fractional form and the bit to the immediate right of the radix point is a one. If it is an unnormalized format, the number is to be represented in fractional form and the bit to the immediate right of the radix point can be either a one or a zero.
If the numbers which are to be processed can be positive or negative, the numeric representation needs to have an encoding scheme to provide the representation of both positive and negative values. Typical encoding methods for integer formats are sign-magnitude, diminished-radix complement (one""s complement for binary or a radix of two) and radix complement (two""s complement for binary or a radix of two). If a floating format is used, both the fraction value and the exponent value may be encoded similar to the integer encoding methods. Furthermore depending upon the range of values and/or accuracy desired, the number of bits (i.e. digits), bytes and words for the numeric representation needs to be considered. For example, the number of bits representing a number may be fixed to one thirty two bit value or four eight bit bytes. As another example, the number of bits representing a number may be thirty two bits for the fractional format and three bits for the exponent.
Additionally, besides a numeric representation, the data type of an instruction set architecture may include character strings or text type of data. The characters in this case are usually encoded into a binary form such as the American Standard Code for Information Interchange (ASCII) code. Another form of encoding is Extended Binary Coded Decimal Interchange Code (EBCDIC). These encoded forms may also be packed from their binary forms into a packed decimal form in order to reduce the number of bits necessary for their representation.
The data type for an instruction set architecture of a digital signal processor (DSP) is important. DSPs generally are distinguished from general purpose microprocessors in that DSPs typically support accelerated arithmetic operations by including a dedicated multiplier and accumulator (MAC) for performing multiplication of digital numbers. The instruction set for a typical DSP device usually includes only one DSP instruction, a MAC instruction, for performing multiplication of new operands and addition with a prior accumulated value stored within an accumulator register. The data type for the operands of the MAC instruction in prior art DSP devices is usually dependent upon the multiplier hardware performing its portion of the MAC operation. Typically the data type is fixed for the DSP. If it is desirable to perform a MAC operation on operands of data having a format that does not conform to the data type, other instructions need be executed to format the data so that it can be processed by the given MAC instruction with the given data type. These other instructions may included reading and writing data into a memory in order to select the appropriate bits of data of the operand upon which to perform the MAC instruction.
One area where DSPs may be utilized is in telecommunication systems. One use of DSPs in telecommunication systems is digital filtering. In this case a DSP is typically programmed with instructions to implement some filter function in the digital or time domain. The mathematical algorithm for a typical finite impulse response (FIR) filter may look like the equation Yn=h0X0+h1X1+h2X2+ . . . +hNXN where hn are fixed filter coefficients numbering from 1 to N and Xn are the data samples. The equation Yn may be evaluated by using a software program. However in some applications, it is necessary that the equation be evaluated as fast as possible. One way to do this is to perform the computations using hardware components such as a DSP device programmed to compute the equation Yn. In order to further speed the process, it is desirable to vectorize the equation and distribute the computation amongst multiple DSPs such that the final result is obtained more quickly. The multiple DSPs operate in parallel to speed the computation process. In this case, the multiplication of terms is spread across the multipliers of the DSPs equally for simultaneous computations of terms. The adding of terms is similarly spread equally across the adders of the DSPs for simultaneous computations. In vectorized processing, the order of processing terms is unimportant since the combination is associative. If the processing order of the terms is altered, it has no effect on the final result expected in a vectorized processing of a function. In a DSP device that is used to perform vectorized processing, it is desirable to consider the type of vectorized processing within the data type of the instruction set architecture to improve data processing efficiency.
Oftentimes the type of filtering used in communication systems differs. The different types of filtering systems may use differing types of operands and filter coefficients. In these cases it is desirable to have flexibility in how DSP instructions process differing operands. It is also desirable to improve the efficiency of using computing resources to speed the execution of DSP instructions.
The present invention is briefly summarized in the claims and includes a method, an apparatus and a system as described therein.